Q: What are edited on the Venice core Athlon 64s (Rev. E) of Winchesters?
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Re:Originally posted by: guy
Originally posted by: d2arcturus
SSE3
ditto, first thing on my mind
SSE3 is one of the more minor updates IMO. It will really only benefit the few apps that support it. The major updates are the improved memory controller and superior manufacturing process. These two factors lead to faster, cooler, mnor eoverclockable chips.
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Re:Originally posted by: d2arcturus
SSE3
ditto, first thing on my mind
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Re:Originally posted by: guy
Originally posted by: guy
Oh I see. So current cores can only support 1T up to 4 banks?
I guess it depends on what you mean by "current". All I know is that the Venice cores, and I suspect the San Diego core, have improved memory controllers that do NOT default 4 sticks of double-sided DDR400 DIMMs from 400MHz to 333MHz but still loosen the timing to 2T from 1T.
Thanks for confirming my understanding. I have a Venice core with 2 x 512MB double-sided dual channel right now. I plan to add another identical pair to give me a total of 2GB DDR 400 dual channel @ 2T (b/c of the 8 banks).
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Re:Originally posted by: guy
Oh I see. So current cores can only support 1T up to 4 banks?
I guess it depends on what you mean by "current". All I know is that the Venice cores, and I suspect the San Diego core, have improved memory controllers that do NOT default 4 sticks of double-sided DDR400 DIMMs from 400MHz to 333MHz but still loosen the timing to 2T from 1T. I believe I've heard that future cores will address this issue but I can't remember which cores and when. Maybe someone here can give us that answer.
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Re:Originally posted by: guy
Originally posted by: guy
SOI has been used since the .13 A64's. It is SS (Strained Silicon) that was evidentally added to the process. NOT SOI.
Jason
Correct, but it wasn't added until San Diego
Winchester = SOI
Venice = DSL
San Diego = SS
Thanks for straightening us out on that daddy but may I ask what DSL stands for – Dual Silicon Layer ??? Just a guess !!!
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Re:Oh I see. So current cores can only support 1T up to 4 banks?
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Re:Originally posted by: guy
3) Support for 4 DDR400 RAM DIMMs that will actually run at 400MHz instead of defaulting to 333MHz like the Pre-Venice Cores and will run the four DDR 400 DIMMs at 1T if one uses Single-Sided RAM – 4 sticks of Double-Sided DDR400 RAM will have to run at 2T
Why will the four single-sided sticks run at 1T but four double-sided sticks will only run at 2T?
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Re:reviews shown better OC w/ venice as well..
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Re:Originally posted by: guy
Correct, but it wasn't added until San Diego
Winchester = SOI
Venice = DSL
San Diego = SS
Right, I didn't think Venice has SS either, only the FX-55 and the SD core has it.
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Re:Originally posted by: guy
SOI has been used since the .13 A64's. It is SS (Strained Silicon) that was evidentally added to the process. NOT SOI.
Jason
Correct, but it wasn't added until San Diego
Winchester = SOI
Venice = DSL
San Diego = SS
Re:SOI has been used since the .13 A64's. It is SS (Strained Silicon) that was evidentally added to the process. NOT SOI.
Jason
Re:I've got my Venice at 2.7 GHz on the stock cooler. I'm gonna get a better one when I have time and might hit 2.8.
Re:According to what I have seen, Venices don't run cooler than Winchesters @ same speed, but they seem to give better o/c.
Re:Originally posted by: guy
Whats been modified on the Venice core Athlon 64s (rev. E) from the Winchester ones?
To my knowledge the four major improvements to the Venice Core A64 I purchased but haven't put into my new system build yet are:
1) Support for Intel's SSE3 instruction set
2) A better/improved memory controller
3) Support for 4 DDR400 RAM DIMMs that will actually run at 400MHz instead of defaulting to 333MHz like the Pre-Venice Cores and will run the four DDR 400 DIMMs at 1T if one uses Single-Sided RAM – 4 sticks of Double-Sided DDR400 RAM will have to run at 2T
4) A Silicon-On-Insulator manufacturing process resulting in:
5) A cooler running CPU and
6) Lower energy consumption
Re:Originally posted by: shoRunner
a "v"
Wrong answer.
Re:No that doesn't cover it, the biggest, most important difference is the silicon-on-insulator manufacturing process that they now use. It runs cooler and consumes less power. This equates to an average overclock for even the 3000+ Venice of 2.6-2.8Ghz on air.
Re:Yup, SSE3, better memory controller, and I believe it usies a different manufacturing process (SOI or something) that results in cooler temps and better OCs.
Re:That pretty much covers it
Re:It also supports 4 RAM dimms @ DDR400 instead of 333, & will do 1T RAM if you can find single-sided RAM.
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